1. Field of the Invention
The present invention relates to an analog circuit, and more particularly to a regulated cascode circuit having a stable operating characteristic at a voltage lower than 1 volt and a CMOS analog circuits including the same.
2. Description of the Related Art
Recently, there has been a trend to design system-on-chip (SoC) devices, as electronic devices rapidly become lighter and thinner to satisfy mobility and portability in a mobile environment.
An integration level of semiconductor integrated circuits has been getting higher, with demand on increased ability to store massive data and multi-functionality. At the same time, there has been an increasing need for low power circuits to reduce battery power consumption. Therefore, most of the circuits are required to operate at a voltage lower than 1 volt due to steady speed-down of the operating voltage.
However, an analog circuit needs higher voltage than a digital circuit, due to limitations of resolution and a physical configuration of analog circuits, which has been an issue in a trend toward miniaturization, and low power consumption.
Nowadays, many problems have been resolved as the result of internal company and laboratory research, so that implementing a low voltage reference or a rail-to-rail input/output circuit can be practically implemented. However, there is not such progress in research for securing a large output impedance and a large swing range.
A leakage current through a gate terminal and a channel length variation are increased by scale down of oxidation thickness and channel length, and thus it is difficult to get a sufficient voltage gain. In addition, a full output swing range of a cascode circuit is difficult to secure at a low operating voltage.
A regulated cascode circuit operating in a weak inversion region has been suggested to solve the above problems, but it is not widely used due to a problem associated with instability of operation.
FIG. 1 is a circuit diagram illustrating a prior art normal cascode circuit, and FIG. 2 is a circuit diagram illustrating a prior art regulated cascade circuit.
A circuit shown in FIG. 1 can increase an output impedance by coupling transistors MN1, MN2 in a stack structure in order to decrease a current variation according to a variation of an output voltage Vo. A sufficient output impedance, however, is difficult to obtain with only the cascode configuration, due to scale-down of semiconductor manufacturing process that cause degradation of characteristic of channel length modulation.
To overcome some of the above disadvantages, a transistor MN3 of a regulated cascode circuit illustrated in FIG. 2 receives a bias voltage from a node “X” to secure an output impedance that is about ten times larger than an output impedance of the normal cascode circuit illustrated in FIG. 1.
The regulated cascode configuration, however, causes additional loss of a swing range, because a threshold voltage becomes twice a threshold voltage of the normal cascode configuration. Therefore, the regulated cascode configuration is inefficient for low voltage operation, i.e., under about 1 volt.
The loss of the swing range of the output voltage can be reduced by causing transistor MN3 to operate in a weak inversion region. In that case, the loss of the swing range of the output voltage can be reduced. Instability of a circuit with respect to temperature variation, however, is increased when the transistor is operated in the weak inversion region, and thus it is difficult to realize a practical circuit.